71. G. S. Lin and you will J. B. Kuo, “Fringing-Induced Thin-Channel-Impression (FINCE) Associated Capacitance Choices of Nanometer FD SOI NMOS Gizmos Having fun with Mesa-Isolation Through https://lovingwomen.org/no/blog/etiopiske-datingsider/ three-dimensional Simulation” , EDSM , Taiwan ,

72. J. B. Kuo, “Evolution from Bootstrap Techniques in Reduced-Voltage CMOS Digital VLSI Circuits for SOC Software” , IWSOC , Banff, Canada ,

P. Yang, “Entrance Misalignment Impact Related Capacitance Choices regarding a 100nm DG FD SOI NMOS Tool which have n+/p+ Poly Most useful/Bottom Door” , ICSICT , Beijing, Asia

73. G. Y. Liu, N. C. Wang and you can J. B. Kuo, “Energy-Productive CMOS Higher-Load Rider Circuit towards Complementary Adiabatic/Bootstrap (CAB) Technique for Lower-Fuel TFT-Lcd Program Applications” , ISCAS , Kobe, Japan ,

74. Y. S. Lin, C. H. Lin, J. B. Kuo and you can K. W. Su, “CGS Capacitance Phenomenon of 100nm FD SOI CMOS Gizmos with HfO2 High-k Door Dielectric Given Straight and you may Fringing Displacement Outcomes” , HKEDSSC , Hong kong ,

75. J. B. KUo, C. H. Hsu and you can C. P. Yang, “Gate-Misalignment Associated Capacitance Conclusion of a great 100nm DG SOI MOS Equipment having N+/p+ Top/Bottom Entrance” , HKEDSSC , Hong kong ,

76. G. Y. Liu, N. C. Wang and J. B. Kuo, “Energy-Productive CMOS Large-Stream Driver Routine to your Subservient Adiabatic/Bootstrap (CAB) Way of Low-Stamina TFT-Lcd System Applications” , ISCAS , Kobe, Japan ,

77. H. P. Chen and you will J. B. Kuo, “A beneficial 0.8V CMOS TSPC Adiabatic DCVS Logic Routine on the Bootstrap Techniques getting Low-Stamina VLSI” , ICECS , Israel ,

B. Kuo, “A manuscript 0

80. J. B. Kuo and you can H. P. Chen, “A low-Voltage CMOS Load Rider towards Adiabatic and you can Bootstrap Suggestions for Low-Power Program Programs” , MWSCAS , Hiroshima, The japanese ,

83. M. T. Lin, Age. C. Sunrays, and you may J. B. Kuo, “Asymmetric Gate Misalignment Effect on Subthreshold Functions DG SOI NMOS Equipment Provided Fringing Electronic Field effect” , Electron Gadgets and Matter Symposium ,

84. J. B. Kuo, E. C. Sunlight, and Meters. T. Lin, “Research out of Door Misalignment Affect new Threshold Current off Twice-Entrance (DG) Ultrathin FD SOI NMOS Products Playing with a tight Design Given Fringing Electronic Field effect” , IEEE Electron Devices getting Microwave oven and Optoelectronic Applications ,

86. Age. Shen and J. 8V BP-DTMOS Content Addressable Memories Mobile Circuit Based on SOI-DTMOS Procedure” , IEEE Conference into Electron Devices and Solid state Circuits , Hong-kong ,

87. P. C. Chen and you will J. B. Kuo, “ic Reasoning Circuit Playing with an immediate Bootstrap (DB) Technique for Low-current CMOS VLSI” , Global Symposium into the Circuits and you can Possibilities ,

89. J. B. Kuo and you can S. C. Lin, “Lightweight Dysfunction Design to possess PD SOI NMOS Gadgets Provided BJT/MOS Impact Ionization for Spice Circuits Simulator” , IEDMS , Taipei ,

ninety. J. B. Kuo and you can S. C. Lin, “Lightweight LDD/FD SOI CMOS Tool Design Given Time Transport and Thinking Temperatures having Liven Circuit Simulation” , IEDMS , Taipei ,

91. S. C. Lin and you can J. B. Kuo, “Fringing-Induced Barrier Reducing (FIBL) Ramifications of 100nm FD SOI NMOS Equipment with high Permittivity Gate Dielectrics and you can LDD/Sidewall Oxide Spacer” , IEEE SOI Conference Proc , Williamsburg ,

ninety-five. J. B. Kuo and you may S. C. Lin, “The newest Fringing Electronic Field-effect on Brief-Channel Impression Endurance Current regarding FD SOI NMOS Equipment that have LDD/Sidewall Oxide Spacer Framework” , Hong kong Electron Gizmos Meeting ,

93. C. L. Yang and you can J. B. Kuo, “High-Temperatures Quasi-Saturation Brand of Large-Current DMOS Strength Equipment” , Hong-kong Electron Devices Meeting ,

94. E. Shen and you will J. B. Kuo, “0.8V CMOS Content-Addressable-Memories (CAM) Mobile Ciurcuit that have a quick Tag-Examine Possibilities Having fun with Vast majority PMOS Dynamic-Endurance (BP-DTMOS) Techniques Considering Practical CMOS Technical to own Lower-Current VLSI Possibilities” , Around the world Symposium towards the Circuits and Systems (ISCAS) Proceedings , Washington ,